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| esmt F59D1G81A / f59d1g161a elite semiconductor memory technology inc. publication date: may 2014 revision: 1.5 1/43 flash 1 gbit (128m x 8/ 64m x 16) 1.8v nand flash memory features ? voltage supply: 1.8v (1.7 v ~ 1.95v) ? organization x8: - memory cell array: (128m + 4m) x 8bit - data register: (2k + 64) x 8bit x16: - memory cell array: (64m + 2m) x 16bit - data register: (1k + 32) x 16bit ? automatic program and erase x8: - page program: (2k + 64) byte - block erase: (128k + 4k) byte x16: - page program: (1k + 32) word - block erase: (64k + 2k) word ? page read operation - page size: (2k + 64) byte (x8) page size: (1k + 32) word (x16) - random read: 25us (max.) - serial access: 45ns (min.) ? memory cell: 1b it/memory cell ? fast write cycle time - program time: 250us (typ.) - block erase time: 2ms (typ.) ? command/address/data multiplexed i/o port ? hardware data protection - program/erase lockout during power transitions ? reliable cmos floating gate technology - ecc requirement: x8 - 1bit/528byte, x16 - 1bit/264word - endurance: 100k program/erase cycles - data retention: 10 years ? command register operation ? automatic page 0 read at power-up option - boot from nand support - automatic memo ry download ? nop: 4 cycles ? cache program operation for high performance operation ? copy-back operation ? edo mode ? otp operation ? no bad-block-erasing-protect function (user should manage bad blocks before erasing) ordering information product id speed package comments x8: F59D1G81A -45tg 45 ns 48 pin tsopi pb-free F59D1G81A -45bg 45 ns 63 ball bga pb-free x16: f59d1g161a -45bg 45 ns 63 ball bga pb-free
esmt F59D1G81A / f59d1g161a elite semiconductor memory technology inc. publication date: may 2014 revision: 1.5 2/43 general description the device is a 128mx8bit with spare 4mx8bit capacity (or 64mx16bit with spare 2mx16bit capacity). the device is offered in 1.8v v cc power supply. its nand cell provides the most cost-effective solution for the solid state mass storage market. the memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. the device contains 1024 blocks, composed by 64 pages consisting in two nand structures of 32 series connected flash cells. a program operation allows to write the 1056-word page in typical 250us and an erase operation can be performed in typical 2ms on a 128k-byte for x8 device block (or 64k-word for x16 device block). data in the page mode can be read out at 45ns cycle time per byte. the i/o pins serve as the ports for address and command inputs as well as data input/output. the copy back function allows the optimization of defe ctive blocks management: when a page program operation fails the data can be directly programmed in another page inside the same array section without the time consuming serial data insertion phase. the cache program feature allows th e data insertion in the cache register while the data register is copied into the flash array. this pipelined program operation improves the program throughput when long files are written inside the memory. a cache read feature is also implem ented. this feature allows to dramatically improving the r ead throughput when consecutive pages have to be streamed out. this device includes extra feature: automatic read at power up. esmt F59D1G81A / f59d1g161a elite semiconductor memory technology inc. publication date: may 2014 revision: 1.5 3/43 pin configuration (x8) (top view) (tsopi 48l, 12mm x 20mm body, 0.5mm pin pitch) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 nc nc nc nc nc nc r/b re ce nc nc v cc v ss nc nc cle ale we wp nc nc nc nc nc 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 nc nc nc nc i/o7 i/o6 i/o5 i/o4 nc nc nc v cc v ss nc nc nc i/o3 i/o2 i/o1 i/o0 nc nc nc nc ball configuration (x8) (top view) (bga 63 ball, 9mm x 11mm body, 0.8 ball pitch) a b c d e f g h j k l m 12345678910 we wp ce re ale r/b v ss v ss v ss v cc v cc i/o0 i/o1 i/o2 i/o3 i/o4 i/o6 i/o5 i/o7 nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc cle esmt F59D1G81A / f59d1g161a elite semiconductor memory technology inc. publication date: may 2014 revision: 1.5 4/43 ball configuration (x16) (top view) (bga 63 ball, 9mm x 11mm body, 0.8 ball pitch) a b c d e f g h j k l m 12345678910 we wp ce re ale r/b v ss v ss v ss v cc v cc i/o0 i/o1 i/o2 i/o3 i/o4 i/o6 i/o5 i/o7 nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc i/o15 nc nc nc nc nc nc i/o13 i/o10 i/o12 nc nc nc nc nc nc nc nc i/o8 i/o9 i/o11 i/o14 cle esmt F59D1G81A / f59d1g161a elite semiconductor memory technology inc. publication date: may 2014 revision: 1.5 5/43 pin description symbol pin name functions i/o0~i/o7 (x8) i/o0~i/o15 (x16) data inputs / outputs the i/o pins are used to input command, address and data, and to output data during read operations. the i/o pins float to hi-z when the chip is deselected or when the outputs are disabled. cle command latch enable the cle input controls the activating path for commands sent to the command register. when active high, commands are latched into the command register through the i/o ports on t he rising edge of the we signal. ale address latch enable the ale input controls the activating path for address to the internal address registers. addresses are latched on the rising edge of we with ale high. ce chip enable the ce input is the device selection cont rol. when the device is in the busy state, ce high is ignored, and the device do es not return to standby mode in program or erase operation. regarding ce control during read operation, refer to ?page read? section of device operation. re read enable the re input is the serial dat a-out control, and when active drives the data onto the i/o bus. data is valid t rea after the falling edge of re which also increments the internal column address counter by one. we write enable the we input controls writes to the i/o port. commands, address and data are latched on the rising edge of the we pulse. wp write protect the wp pin provides inadvertent program/erase protection during power transitions. the internal high voltage generator is reset when the wp pin is active low. r / b ready / busy output the r/ b output indicates the status of t he device operation. when low, it indicates that a program, erase or ran dom read operation is in process and returns to high state upon completion. it is an open drain output and does not float to hi-z condition when the chip is deselected or when outputs are disabled. v cc power v cc is the power supply for device. v ss ground nc no connection lead is not internally connected. note: connect all v cc and v ss pins of each device to common powe r supply outputs. do not leave v cc or v ss disconnected. esmt F59D1G81A / f59d1g161a elite semiconductor memory technology inc. publication date: may 2014 revision: 1.5 6/43 block diagram (x8) array organization (x8) address cycle map (x8) i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 1st cycle a0 a1 a2 a3 a4 a5 a6 a7 column address 2nd cycle a8 a9 a10 a11 l* l* l* l* column address 3rd cycle a12 a13 a14 a15 a16 a17 a18 a19 row address 4th cycle a20 a21 a22 a23 a24 a25 a26 a27 row address note: column address: starting address of the register. *l must be set to ?low?. * the device ignores any additional input of address cycles than required. esmt F59D1G81A / f59d1g161a elite semiconductor memory technology inc. publication date: may 2014 revision: 1.5 7/43 block diagram (x16) array organization (x16) address cycle map (x16) i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 i/o8~i/o15 1st cycle a0 a1 a2 a3 a4 a5 a6 a7 l* column address 2nd cycle a8 a9 a10 l* l* l* l* l* l* column address 3rd cycle a11 a12 a13 a14 a15 a16 a17 a18 l* row address 4th cycle a19 a20 a21 a22 a23 a24 a25 a26 l* row address note: column address: starting address of the register. *l must be set to ?low?. * the device ignores any additional input of address cycles than required. esmt F59D1G81A / f59d1g161a elite semiconductor memory technology inc. publication date: may 2014 revision: 1.5 8/43 product introduction the device is a 1,056mbit memory organized as 64k rows (pages) by 2,112x8 columns. spare 64x8 columns are located from column address of 2,048~2,111. a 2,112-byte data register is connected to memory cell a rrays accommodating data transfer between the i /o buffers and memory during page read and page program operations. the program and read operations are executed on a page basis, while the erase operation is executed on a block basis. the memory array consists of 1,024 separately erasable 128k-byte blocks . it indicates that the bit-by-bit erase op eration is prohibit ed on the device. the device has addresses multiplexed into 8 i/os or 16i/os. this scheme dramatically reduces pin counts and allows system upgra des to future densities by maintaining cons istency in system board design. command, address and data are all written through i/o's by bringing we to low while ce is low. those are latched on the rising edge of we . command latch enable (cle) and address latch enable (ale) are used to multiplex command and address respectively, via the i/o pins. some commands require one bus cycl e. for example, reset command, status read command, etc require just one cycle bus. some other commands, like page read and block erase and page program, require two cycles: one cycle for setup and the other cycle for execution. in addition to the enhanced architecture an d interface, the device incorporates copy -back program feature from one page to anot her page without need for transporting the data to and from the external buffer memory. command set function 1st cycle 2nd cycle acceptable command during busy read 00h 30h read for copy back 00h 35h read id 90h - reset ffh - o page program 80h 10h copy-back program 85h 10h block erase 60h d0h random data input (1) 85h - random data output (1) 05h e0h read status 70h - o cache program 80h 15h cache read 31h - read start for last page cache read 3fh - note: 1. random data input / output can be executed in a page. esmt F59D1G81A / f59d1g161a elite semiconductor memory technology inc. publication date: may 2014 revision: 1.5 9/43 absolute maximum ratings parameter symbol rating unit v cc -0.6 to +2.45 v in -0.6 to +2.45 voltage on any pin relative to v ss v i/o -0.6 to v cc + 0.3 (< 2.45) v temperature under bias t bias -40 to +125 storage temperature t stg -65 to +150 short circuit current i os 5 ma note: 1. permanent device damage may occur if absolute maximu m ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect reliability. recommended operating conditions (voltage reference to gnd, t a = 0 to 70 ) parameter symbol min. typ. max. unit supply voltage v cc 1.7 1.8 1.95 v supply voltage v ss 0 0 0 v dc and operation char acteristics (recommended operating conditions otherwise noted) parameter symbol test conditions min. typ. max. unit page read with serial access i cc1 t rc =45ns, ce =v il , i out =0ma - 15 program i cc2 - - 15 operating current erase i cc3 - - 15 30 ma stand-by current (ttl) i sb1 ce =v ih , wp =0v/v cc - - 1 ma stand-by current (cmos) i sb2 ce = v cc -0.2, wp =0v/ v cc - 10 50 ua input leakage current i li v in =0 to v cc (max) - - 10 ua output leakage current i lo v out =0 to v cc (max) - - 10 ua input high voltage v ih (1) - 0.8 x v cc - v cc +0.3 v input low voltage, all inputs v il (1) - -0.3 - 0.2 x v cc v output high voltage level v oh i oh =-100ua v cc - 0.1 - - v output low voltage level v ol i ol =+100ua - - 0.1 v output low current (r/b) i ol (r / b ) v ol =0.1v 3 4 - ma note: 1. v il can undershoot to -0.4v and v ih can overshoot to v cc +0.4v for durations of 20ns or less. 2. typical value are measured at v cc =1.8v, t a =25 . and not 100% tested. valid block symbol min. typ. max. unit n vb 1,004 - 1,024 blocks note: 1. the device may include initial invalid blocks when first ship ped. the number of valid blocks is presented as first shipped. do not erase or program factory-marked bad blocks. refer to the attac hed technical notes for appropriate management of initial invalid blocks. 2. the 1st block, which is placed on 00h bl ock address, is guaranteed to be a valid blo ck at the time of shipment and is guaran teed to be a valid block up to 1k program/erase cycles with 1bit/528byte (or 1 bit/264word) ecc. esmt F59D1G81A / f59d1g161a elite semiconductor memory technology inc. publication date: may 2014 revision: 1.5 10/43 ac test condition (t a =0 to 70 , v cc =1.7v~1.95v) parameter condition input pulse levels 0v to v cc input rise and fall times 5 ns input and output timing levels v cc /2 output load 1 ttl gate and c l =30pf note: * refer to ready / busy section, r/b output?s busy to ready ti me is decided by the pull-up resistor (r p ) tied to r/ b pin. capacitance (t a =25 , v cc =1.8v, f=1.0mhz) item symbol test condition min. max. unit input / output capacitance c i/o v il = 0v - 10 pf input capacitance c in v in = 0v - 10 pf note: capacitance is periodically sampled and not 100% tested. mode selection cle ale ce we re wp mode h l l h x command input l h l h x read mode address input (4 clock) h l l h h command input l h l h h write mode address input (4 clock) l l l h h data input l l l h x data output x x x x h x during read (busy) x x x x x h during program (busy) x x x x x h during erase (busy) x x (1) x x x l write protect x x h x x 0v/v cc (2) stand-by note: 1. x can be v il or v ih . 2. wp should be biased to cmos high or cmos low for stand-by. esmt F59D1G81A / f59d1g161a elite semiconductor memory technology inc. publication date: may 2014 revision: 1.5 11/43 program / erase characteristics (t a =0 to 70 , v cc =1.7v~1.95v) parameter symbol min. typ. max. unit program time t prog - 250 700 us dummy busy time for cache program t cbsy - 3 700 us number of partial program cycles in the same page n op - - 4 cycle block erase time t bers - 2 10 ms note: 1. typical program time is defined as the time within which more than 50% of the whole pages are programmed at 1.8v v cc and 25 temperature. 2. t prog is the average program time of all pages. users should be not ed that the program time variation from page to page is possible. 3. t cbsy max. time depends on timing between internal program completion and data in. ac timing characteristics for command / address / data input parameter symbol min. max. unit cle setup time t cls (1) 25 - ns cle hold time t clh 10 - ns ce setup time t cs (1) 35 - ns ce hold time t ch 10 - ns we pulse width t wp 25 - ns ale setup time t als (1) 25 - ns ale hold time t alh 10 - ns data setup time t ds (1) 20 - ns data hold time t dh 10 - ns write cycle time t wc 45 - ns we high hold time t wh 15 - ns ale to data loading time t adl (2) 100 - ns note: 1. the transition of the corresponding control pins must occur only once while we is held low. 2. t adl is the time from the we rising edge of final address cycle to the we rising edge of first data cycle. esmt F59D1G81A / f59d1g161a elite semiconductor memory technology inc. publication date: may 2014 revision: 1.5 12/43 ac characteristics for operation parameter symbol min. max. unit data transfer from cell to register t r - 25 us ale to re delay t ar 10 - ns cle to re delay t clr 10 - ns ready to re low t rr 20 - ns re pulse width t rp 25 - ns we high to busy t wb - 100 ns wp low to we low (disable mode) wp high to we low (enable mode) t ww 100 - ns read cycle time t rc 45 - ns re access time t rea - 30 ns ce access time t cea - 45 ns re high to output hi-z t rhz - 100 ns ce high to output hi-z t chz - 30 ns ce high to ale or cle don?t care t csd 0 - ns re high to output hold t rhoh 15 - ns re low to output hold t rloh 5 - ns ce high to output hold t coh 15 - ns re high hold time t reh 15 - ns output hi-z to re low t ir 0 - ns re high to we low t rhw 100 - ns we high to re low t whr 60 - ns read - 5 us program - 10 us erase - 500 us device resetting time during ... ready t rst - 5 (1) us cache busy in read cache (following 31h and 3fh) t dcbsyr - 30 us note: 1. if reset command (ffh) is written at ready state, the device goes into busy for maximum 5us. esmt F59D1G81A / f59d1g161a elite semiconductor memory technology inc. publication date: may 2014 revision: 1.5 13/43 nand flash technical notes mask out initial invalid block(s) initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by esmt. the information regarding the initial invalid block(s) is called as the initial invalid block information. devices with initial inv alid block(s) have the same quality level as devices with all valid blocks and have the same ac and dc characteristics. an initial invalid block(s ) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select transi stor. the system design must be able to mask out the initial invalid block(s) via address mapping. the 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1k program/erase cycles with 1 bit/528byte (1 bit/264word) ecc. identifying initial invalid block(s) and block replacement management all device locations are erased (ffh) except locations where the initial invalid block(s) information is written prior to shipp ing. the initial invalid block(s) status is defined by the 1st byte in the spare area. esmt makes sure that either the 1st or 2nd page of every initial invalid block has non-ffh data at the 1st byte column address in the spare area. since the initial invalid block information is also erasable in most cases, it is impossible to recover the information once it has been erased. therefore, the system must be able to recognize the initial invalid block(s) based on the initial invalid block information and create the initial invalid block tabl e via the following suggested flow chart. any intentional erasure of the initial invalid block information is prohibited. esmt F59D1G81A / f59d1g161a elite semiconductor memory technology inc. publication date: may 2014 revision: 1.5 14/43 algorithm for bad block scanning for (i=0; i esmt F59D1G81A / f59d1g161a elite semiconductor memory technology inc. publication date: may 2014 revision: 1.5 16/43 erase flow chart read flow chart esmt F59D1G81A / f59d1g161a elite semiconductor memory technology inc. publication date: may 2014 revision: 1.5 17/43 block replacement addressing for program operation within a block, the pages must be programmed consecutively from the lsb (least significant bit) page of the block to msb (most significant bit) pages of the block. random page address programming is prohibited. in this case, the definition of lsb page is the lsb among the pages to be programmed. therefore, lsb page doesn?t need to be page 0. esmt F59D1G81A / f59d1g161a elite semiconductor memory technology inc. publication date: may 2014 revision: 1.5 18/43 system interface using ce don?t care for an easier system interface, ce may be inactive during the data-loading or serial access as shown below. the internal 2,112byte (1,056word) data registers are utilized as separate buffers for this operation and the system design gets more flexible. in add ition, for voice or audio applications that use slow cycle time on the order of -seconds, de-activating ce during the data-loading and serial access would provide significant savings in power consumption. program / read operation with ? ce not-care? address information data i/o address device data in/out i/ox col. add1 co l. add2 row add1 row add2 F59D1G81A (1gb x8) 2,112 byte i/o 0 ~ i/o 7 a0 ~ a7 a8 ~ a11 a12 ~ a19 a20 ~ a27 f59d1g161a (1gb x16) 1,056 word i/o 0 ~ i/o 15 a0 ~ a7 a8 ~ a10 a11 ~ a18 a19 ~ a26 esmt F59D1G81A / f59d1g161a elite semiconductor memory technology inc. publication date: may 2014 revision: 1.5 19/43 timing diagrams command latch cycle address latch cycle input data latch cycle esmt F59D1G81A / f59d1g161a elite semiconductor memory technology inc. publication date: may 2014 revision: 1.5 20/43 serial access cycle after read (cle = l, we = h, ale = l) note : 1. dout transition is measured at 200mv from steady state voltage at i/o with load. 2. t rhoh starts to be valid when frequency is lower than 20mhz. serial access cycle after read (edo type cle = l, we = h, ale = l) note : 1. transition is measured at +/-200mv from steady state voltage with load. this parameter is sample and not 100% tested. (t chz , t rhz ) 2. t rloh is valid when frequency is higher than 33mhz. t rhoh starts to be valid when frequency is lower than 33mhz. status read cycle esmt F59D1G81A / f59d1g161a elite semiconductor memory technology inc. publication date: may 2014 revision: 1.5 21/43 read operation read operation (intercepted by ce ) esmt F59D1G81A / f59d1g161a elite semiconductor memory technology inc. publication date: may 2014 revision: 1.5 22/43 random data output in a page page program operation note : t adl is the time from the we rising edge of final address cycle to the we rising edge of the first data cycle. esmt F59D1G81A / f59d1g161a elite semiconductor memory technology inc. publication date: may 2014 revision: 1.5 23/43 page program operation with random data input note : t adl is the time from the we rising edge of final address cycle to the we rising edge of the first data cycle. copy-back operation with random data input esmt F59D1G81A / f59d1g161a elite semiconductor memory technology inc. publication date: may 2014 revision: 1.5 24/43 cache program operation cache read operation esmt F59D1G81A / f59d1g161a elite semiconductor memory technology inc. publication date: may 2014 revision: 1.5 25/43 block erase operation read id operation esmt F59D1G81A / f59d1g161a elite semiconductor memory technology inc. publication date: may 2014 revision: 1.5 26/43 id definition table id access command = 90h product id 1 st cycle (maker code) 2 nd cycle (device code) 3 rd cycle 4 th cycle 5 th cycle F59D1G81A (x8) c8h a1h 80h 15h 40h f59d1g161a (x16) c8h b1h 80h 55h 40h description 1 st byte maker code 2 nd byte device code 3 rd byte internal chip number, cell type, etc. 4 th byte page size, block size, etc. 5 th byte plane number, plane size, ecc level 3rd id data item description i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 1 0 0 2 0 1 4 1 0 internal chip number 8 1 1 2 level cell 0 0 4 level cell 0 1 8 level cell 1 0 cell type 16 level cell 1 1 1 0 0 2 0 1 4 1 0 number of simultaneously programmed page 8 1 1 not support 0 interleave program between multiple chips support 1 not support 0 cache program support 1 4th id data item description i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 1kb 0 0 2kb 0 1 4kb 1 0 page size (w/o redundant area) 8kb 1 1 8 0 redundant area size (byte/512byte) 16 1 64kb 0 0 128kb 0 1 256kb 1 0 block size (w/o redundant area) 512kb 1 1 x8 0 organization x16 1 45ns 0 0 reserved 0 1 reserved 1 0 serial access time reserved 1 1 esmt F59D1G81A / f59d1g161a elite semiconductor memory technology inc. publication date: may 2014 revision: 1.5 27/43 5th id data item description i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 1bit ecc/512byte 0 0 2bit ecc/512byte 0 1 4bit ecc/512byte 1 0 ecc level reserved 1 1 1 0 0 2 0 1 4 1 0 plane number 8 1 1 64mb 0 0 0 128mb 0 0 1 256mb 0 1 0 512mb 0 1 1 1gb 1 0 0 2gb 1 0 1 4gb 1 1 0 plane size (w/o redundant area) 8gb 1 1 1 reserved reserved 0 esmt F59D1G81A / f59d1g161a elite semiconductor memory technology inc. publication date: may 2014 revision: 1.5 28/43 device operation page read upon initial device power up, the device defaults to read mode. this operation is also initiated by writing 00h command, four-c ycle address, and 30h command. after initial power up, the 00h command can be skipped because it has been latched in the command register. the 2,112byte (1,056word) of data on a page are transferred to cache registers via data registers within 25us (t r ). host controller can detect the completion of this data transfer by checking the r/ b output. once data in the selected page have been loaded into cache registers, each byte can be read out in 45ns cycle time by continuously pulsing re . the repetitive high-to-low transitions of re clock signal make the device output data starting from the designated column address to the last column address. the device can output data at a random column address instead of sequential column address by using the random data output command. random data output command can be executed multiple times in a page. after power up, device is in read mode so 00h command cycle is not necessary to start a read operation. a page read sequence is illustrated in under figure, where column address, page address are placed in between commands 00h and 30h. after t r read time, the r/ b de-asserts to ready state. host controller can toggle re to access data starting with the designated column address and their successive bytes. read operation esmt F59D1G81A / f59d1g161a elite semiconductor memory technology inc. publication date: may 2014 revision: 1.5 29/43 random data output in a page esmt F59D1G81A / f59d1g161a elite semiconductor memory technology inc. publication date: may 2014 revision: 1.5 30/43 page program the device is programmed basically on a page basis, but it does allow multiple partial page programming of a word or consecutiv e bytes up to 2,112(x8) or words up to 1,056(x16), in a single page program cycle. the number of consecutive partial page program ming operation within the same page without an intervening erase operation must not exceed 4 times for a single page. addressing of page program operations within a block should be in sequential order. a complete page program cycle consists of a serial data i nput cycle in which up to 2,112byte (1,056word) of data can be loaded into data register via cache register, followed by a programmi ng period during which the loaded data are programmed into the designated memory cells. the serial data input cycle begins with the serial data input command (80h), followed by a four-cycle address input and then se rial data loading. the bytes not to be programmed on the page do not need to be loaded. the column address for the next data can be changed to the address follows random data input command (85h). random data input command may be repeated multiple times in a page. the page program confirm command (10h) starts the programming process. writing 10h alone without entering data will not initiate the programming process. the internal write engine automatically executes the corresponding algorithm and controls tim ing for programming and verification, thereby free ing the host controller for other tasks. once the program process starts, the host co ntroller can detect the completion of a program cycle by monitoring the r/ b output or reading the status bit (i/o6) using the read status command. only read status and reset commands are valid during programming. when the page program operation is completed, the host controller can check the status bit (i/o0) to see if the page program operation is successfully done. the command regi ster remains the read status mode unless another valid command is written to it. a page program sequence is illustrated in under figure, where column address, page add ress, and data input are placed in betwee n 80h and 10h. after t prog program time, the r/ b de-asserts to ready state. read status command (70h) can be issued right after 10h. program & read status operation random data input in a page esmt F59D1G81A / f59d1g161a elite semiconductor memory technology inc. publication date: may 2014 revision: 1.5 31/43 cache program cache program is an extension of page program, which is executed with 2,112 bytes (x8) or 1,056 words (x16) data registers, and is available only within a block. since the device has 1 page of cache memory, serial data input may be executed while data stored in data register are programmed into memory cell. after writing the first set of data up to 2,112 bytes (x8) or 1,056 words (x16) into the selected cache registers, cache progra m command (15h) instead of actual page program (10h) is inputted to make cache registers free and to start internal program opera tion. to transfer data from cache registers to data registers, the device remains in busy state for a short period of time (t cbsy ) and has its cache registers ready for the next data-input while the internal programming gets started with the data loaded into data regist ers. read status command (70h) may be issued to find out when cache regist ers become ready by polling the cache-busy status bit (i/o6). pass/fail status of only the previous page is available upon the return to ready state. when the next set of data is inputted w ith the cache program command, t cbsy is affected by the progress of pending internal programming. the programming of the cache registers is initiated only when the pending program cycle is finished and the data registers are available for the transfer of data from cache registers. the status bit (i/o5) for internal ready/busy may be polled to identity the completion of internal programming. if t he system monitors the progress of programming only with r/ b , the last page of the target programming sequence must be programmed with actual page program command (10h). cache program (available only within a block) note: 1. since programming the last page does not employ caching, the program time has to be that of page program. however, if the previous program cycle with the cache data has not finished, the actual program cycle of the last page is initiated only after completion of the previous cycle, which can be expressed as the following formula. 2. t prog = program time for the last page + program time for the (last-1)th page ? (program command cycle time + last page data loading time) esmt F59D1G81A / f59d1g161a elite semiconductor memory technology inc. publication date: may 2014 revision: 1.5 32/43 copy-back program copy-back program is designed to efficiently copy data stored in memory cells without time-consuming data reloading when there is no bit error detected in the stored data. the benefit is particularly obvious when a portion of a block is updated and the rest of the block needs to be copied to a newly assigned empty block. copy-back operation is a sequential execution of read for copy-back and of copy-back program with destination address. a read for copy-b ack operation with ?35h? command and the source address moves the whole 2,112byte (1,056word) data into the internal buffer. the host controller can detect bit errors by sequentially readin g the data output. copy-back program is initiated by issuing page-copy data-input command (85h) with destination address. if data modifica tion is necessary to correct bit errors and to avoid error propagation, data can be reloaded after the destination address. data mod ification can be repeated multiple times as shown in under figure. act ual programming operation begins when program confirm command (10h) is issued. once the program process starts, the read status co mmand (70h) may be entered to read the status register. the host controller can detect the completion of a program cycle by monitoring the r/ b output, or the status bit (i/o6) of the status register. when the copy-back program is complete, the status bit (i/o0) may be checked. the command register remains read status mode until another valid command is written to it. page copy-back program operation page copy-back program operation with random data input esmt F59D1G81A / f59d1g161a elite semiconductor memory technology inc. publication date: may 2014 revision: 1.5 33/43 block erase the block-based erase operation is initiated by an erase setup command (60h), followed by a two-cycle row address, in which onl y plane address and block address are valid while page address is ignored. the erase confirm command (d0h) following the row address starts the internal erasing process. the two-step comma nd sequence is designed to prevent memory content from being inadvertently changed by external noise. at the rising edge of we after the erase confirm command input, the internal control logic handles erase and erase-verify. when the erase operation is complete d, the host controller can check status bit (i/o0) to see i f the erase operation is successfully done. the under figure illustrat es a block erase sequence, and the address input (the first pag e address of the selected block) is placed in between commands 60h and d0h. after t bers erase time, the r/ b de-asserts to ready state. read status command (70h) can be issued right after d0h to check the execution status of erase operation. block erase operation read status a status register on the device is used to check whether progr am or erase operation is completed and whether the operation is completed successfully. after writing 70h command to the command register, a read cycle outputs the content of the status regis ter to i/o pins on the falling edge of ce or re , whichever occurs last. the command allows the system to poll the progress of each device in multiple memory connections even when r/ b pins are common-wired. re or ce does not need to toggle for status change. read status command 70h is used to retrieve operating status of commands like page read, page program and block erase. the command register remains in read status mode unless other commands are issued to it. therefore, if the status register is r ead during a random read cycle, a read command (00h) is needed to start read cycles. status register definition for 70h command i/o page program block erase read cache read definition i/o0 pass / fail pass / fail na na pass: 0 fail: 1 i/o1 na na na na don?t cared i/o2 pass/fail (for otp) na na na don?t cared i/o3 na na na na don?t cared i/o4 na na na na don?t cared i/o5 na na na true ready / busy busy: 0 ready: 1 i/o6 ready / busy ready / busy ready / busy ready / busy busy: 0 ready: 1 i/o7 write protect write protect write protect write protect protected: 0 not protected: 1 note: i/os defined ?na? are recommended to be masked out when read status is being executed. esmt F59D1G81A / f59d1g161a elite semiconductor memory technology inc. publication date: may 2014 revision: 1.5 34/43 read id the device contains a product identification mode, initiated by writing 90h to the command register, followed by an address inp ut of 00h. four read cycles sequentially output the manufacturer code (c8h) , and the device code and 3rd, 4th, 5th cycle id respectively. the command register remains in read id mode until further commands are issued to it. read id operation id definition table product id 1 st cycle (maker code) 2 nd cycle (device code) 3 rd cycle 4 th cycle 5 th cycle F59D1G81A (x8) c8h a1h 80h 15h 40h f59d1g161a (x16) c8h b1h 80h 55h 40h reset the device offers a reset feature, executed by writing ffh to the command register. when the device is in busy state during ran dom read, program or erase mode, the reset operation will abort these operations. the contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. the command register is cleared to wait for the next command, and th e status register is cleared to value c0h when wp is high. if the device is already in reset state a new reset command will be accepted by the command register. the r/ b pin changes to low for t rst after the reset command is written. refer to the figure below. reset operation device status table after power-up after reset operation mode 00h command is latched waiting for next command esmt F59D1G81A / f59d1g161a elite semiconductor memory technology inc. publication date: may 2014 revision: 1.5 35/43 cache read cache read is an extension of page read, and is available only within a block. the normal page read command (00h-30h) is always issued before invoking cache read. after issuing the cache read command (31h), read data of the designated page (page n) are transferred from data registers to cache registers in a short time period of t dcbsyr , and then data of the next page (page n+1) is transferred to data registers while the data in the cache regist ers are being read out. host controller can retrieve continuous data and achieve fast read performance by iterating cache read operation. the read start for last page cache read command (3fh) is used to complete data transfer from memory cells to data registers. read operation with cache read esmt F59D1G81A / f59d1g161a elite semiconductor memory technology inc. publication date: may 2014 revision: 1.5 36/43 ready / busy the device has a r/ b output that provides a hardware method of indicating the completion of a page program, erase and random read completion. the r/ b pin is normally high but transition to low after pr ogram or erase command is written to the command register or random read is started after address loading. it returns to high when the internal controller has finished the oper ation. the pin is an open-drain driver thereby allowing two or more r/ b outputs to be or-tied. because pull-up resistor value is related to tr (r/ b ) and current drain during busy (ibusy), an appropriate value can be obtained with the following reference chart. its value can b e determined by the following guidance. ready/ busy pin electrical specifications where il is the sum of the iput currents of all devices tied to the r/ b pin. rp(max) is determined by maximum permissible limit of tr esmt F59D1G81A / f59d1g161a elite semiconductor memory technology inc. publication date: may 2014 revision: 1.5 37/43 data protection & power up sequence the timing sequence shown in the figure below is necessary for the power-on/off sequence. the device internal initialization starts after the power supply reaches an appropriate level in the power on sequence. during the initialization the device r/ b signal indicates the busy state as shown in the figure below. in this time period, the acceptable commands are 70h. the wp signal is useful for protecting against data corruption at power on/off. ac waveforms for power transition write protect operation enabling wp during erase and program busy is prohibited. the erase and program operations are enabled and disabled as follows: enable programming note : wp keeps ?high? until programming finish. esmt F59D1G81A / f59d1g161a elite semiconductor memory technology inc. publication date: may 2014 revision: 1.5 38/43 disable programming enable erasing note : wp keeps ?high? until erasing finish. disable erasing esmt F59D1G81A / f59d1g161a elite semiconductor memory technology inc. publication date: may 2014 revision: 1.5 39/43 one-time programmable (otp) operations this flash device offers one-time programmable memory area. th irty full pages of otp data are available on the device, and the entire range is guaranteed to be good. the otp area is accessible only through the otp commands. the otp area leaves the factory in an unwritten state. the otp area cannot be erased, whether it is protected or not. protectin g the otp area prevents further programming of that area. the otp area is only accessible while in otp operation mode. to set the device to otp operation mode, issue the set feature (efh-90h-01h) command. when the device is in otp operation mode, subsequent read and/or page program are applied to the otp area. when you want to come back to normal operation, you ne ed to use efh-90h-00h for otp mode release. otherwise, device will stay in otp mode. to program an otp page, issue the serial data input (80h) command followed by 4 address cycles. the first two address cycles ar e column address that must be set as 00h. for the third cycle, select a page in the range of 01h through 1eh. the fourth cycle is fixed at 00h. next, up to 2,112 bytes of data can be loaded into data register. the bytes other than those to be programmed do not need to be loaded. random data input (85h) command in this device is prohibited. the page program confirm (10h) command initiates the programming process. the internal control logic automatically executes the programming algorithm, timing and verification. plea se note that no partial-page program is allowed in the otp area. in addition, the otp pages must be programmed in the ascending or der. a programmed otp page will be automatically protected. similarly, to read data from an otp page, set the device to ot p operation mode and then issue the read (00h-30h) command. the device may output random data (not in sequential order) in a page by writing random data output (05h-e0h) command, which can be operated multiple times in a page. the column address for the next data to be output may be changed to the address follows the random data output command. all pages in the otp area will be protected simultaneously by i ssuing the set feature (efh-90h-03h) command to set the device t o otp protection mode. after the otp area is protected, no pag e in the area is programmable and the whole area cannot be unprotected. the read status (70h) command is the only valid command for reading status in otp operation mode. otp modes and commands set feature command read efh-90h 1 -01h 2 00h-30h otp operation mode page program efh-90h-01h 80h-10h otp protection mode program protect efh-90h-03h 80h-10h otp release mode leave otp mode efh-90h-00h note: 1. 90h is otp status register address. 2. 00h, 01h and 03h are otp status register data values. otp area details description value number of otp pages 30 otp page address 01h ? 1eh number of partial page programs for each page in the otp area 1 esmt F59D1G81A / f59d1g161a elite semiconductor memory technology inc. publication date: may 2014 revision: 1.5 40/43 packing dimension 48-lead tsop(i) ( 12x20 mm ) dimension in mm dimension in inch dimension in mm dimension in inch symbol min norm max min norm max symbol min norm max min norm max a ------- ---- --- 1.20 ------- -- ----- 0.047 d 20.00 bsc 0.787 bsc a 1 0.05 ------- 0.15 0.006 ------- 0.002 d 1 18.40 bsc 0.724 bsc a 2 0.95 1.00 1.05 0.037 0.039 0. 041 e 12.00 bsc 0.472 bsc b 0.17 0.22 0.27 0.007 0.009 0.011 e 0.50 bsc 0.020 bsc b1 0.17 0.20 0.23 0.007 0.008 0.009 l 0.50 0.60 0.70 0.020 0.024 0.028 c 0.10 ------- 0.21 0.004 ------- 0.008 0 o ------- 8 o 0 o ------- 8 o c1 0.10 ------- 0. 16 0.004 ------- 0.006 esmt F59D1G81A / f59d1g161a elite semiconductor memory technology inc. publication date: may 2014 revision: 1.5 41/43 packing dimensions 63-ball 1g nand flash ( 9x11 mm ) a2 a1 a seating plane cccc c solder ball b pin #1 pin #1 index detail b detail a detail a detail b e e e e d1 e1 d e dimension in mm dimension in inch symbol min norm max min norm max a 1.00 0.039 a 1 0.25 0.35 0.010 0.014 a 2 0.60 bsc 0.024 bsc b 0.40 0.50 0.016 0.020 d 10.90 11.00 11.10 0.429 0.433 0.437 e 8.90 9.00 9.10 0.350 0.354 0.358 d 1 8.80 bsc 0.346 bsc e 1 7.20 bsc 0.283 bsc e 0.8 bsc 0.031 bsc ccc 0.10 0.004 controlling dimension : millimeter. esmt F59D1G81A / f59d1g161a elite semiconductor memory technology inc. publication date: may 2014 revision: 1.5 42/43 revision history revision date description 0.1 2011.09.09 original 0.2 2011.12.05 1. add more description 2. correct otp page address 1.0 2012.03.19 1. delete "preliminary" 2. add bga package 3. update the value of tbd 4. correct typo 1.1 2012.11.30 add f59d1g161a product 1.2 2012.12.12 correct h3 ball of bga ball configuration (x16) 1.3 2013.05.02 1. correct the description of page program 2. add "no bad-block-erasing-protect function" 1.4 2013.07.19 modify the description of read status and otp operations 1.5 2014.05.21 modify the description of identifying initial invalid block(s) and block replacement management esmt F59D1G81A / f59d1g161a elite semiconductor memory technology inc. publication date: may 2014 revision: 1.5 43/43 important notice all rights reserved. no part of this document may be reproduced or duplicated in any form or by any means without the prior permission of esmt. the contents contained in this docum ent are believed to be accurate at the time of publication. esmt assu mes no responsibilit y for any error in this document, and reserves the right to change the products or specification in this document without notice. the information contained herein is presented only as a guide or examples for the application of o ur products. no responsibility is assumed by esmt for any infringement of patents, copyrights, or other intellectual property rights of third part ies which may result from its use. no license, either express , implied or otherwise, is granted under any patents, copyrights or other inte llectual property rights of esmt or others. any semiconductor devices may have i nherently a certain rate of failure. to minimize risks associated with customer's application, adequate design and operating safeguards agains t injury, damage, or loss from such failure, should be provided by the customer when making application designs. esmt's products are not authorized for us e in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. if products described here are to be used for such kinds of applicatio n, purchaser must do its own quality assurance testing appropriate to such applications. |
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